? semiconductor components industries, llc, 2002 june, 2002 rev. 5 1 publication order number: mc14555b/d mc14555b, mc14556b dual binary to 1-of-4 decoder/demultiplexer the mc14555b and mc14556b are constructed with complementary mos (cmos) enhancement mode devices. each decoder/demultiplexer has two select inputs (a and b), an active low enable input (e), and four mutually exclusive outputs (q0, q1, q2, q3). the mc14555b has the selected output go to the ahigho state, and the mc14556b has the selected output go to the alowo state. expanded decoding such as binarytohexadecimal (1of16), etc., can be achieved by using other mc14555b or mc14556b devices. applications include code conversion, address decoding, memory selection control, and demultiplexing (using the enable input as a data input) in digital data transmission systems. ? diode protection on all inputs ? active high or active low outputs ? expandable ? supply voltage range = 3.0 vdc to 18 vdc ? all outputs buffered ? capable of driving two lowpower ttl loads or one lowpower schottky ttl load over the rated temperature range maximum ratings (voltages referenced to v ss ) (note 2) symbol parameter value unit v dd dc supply voltage range 0.5 to +18.0 v v in , v out input or output voltage range (dc or transient) 0.5 to v dd + 0.5 v i in , i out input or output current (dc or transient) per pin 10 ma p d power dissipation, per package (note 3) 500 mw t a ambient temperature range 55 to +125 c t stg storage temperature range 65 to +150 c t l lead temperature (8second soldering) 260 c 2. maximum ratings are those values beyond which damage to the device may occur. 3. temperature derating: plastic ap and d/dwo packages: 7.0 mw/ c from 65 c to 125 c this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this highimpedance circuit. for proper operation, v in and v out should be constrained to the range v ss (v in or v out ) v dd . unused inputs must always be tied to an appropriate logic voltage level (e.g., either v ss or v dd ). unused outputs must be left open. x = specific device code a = assembly location wl, l = wafer lot yy, y = year ww, w = work week device package shipping ordering information mc14555bcp pdip16 2000/box mc14555bd soic16 48/rail mc14555bdr2 soic16 2500/tape & reel 1. for ordering information on the eiaj version of the soic packages, please contact your local on semiconductor representative. marking diagrams 1 16 pdip16 p suffix case 648 mc1455xbcp awlyyww soic16 d suffix case 751b 1 16 1455xb awlyww soeiaj16 f suffix case 966 1 16 mc1455xb alyw mc14555bfel soeiaj16 see note 1 mc14555bf soeiaj16 see note 1 mc14556bcp pdip16 2000/box mc14556bd soic16 48/rail mc14556bdr2 soic16 2500/tape & reel mc14556bf soeiaj16 see note 1 http://onsemi.com
mc14555b, mc14556b http://onsemi.com 2 pin assignments 13 14 15 16 9 10 11 12 5 4 3 2 1 8 7 6 q0 b b b a b e b v dd q3 b q2 b q1 b q0 a b a a a e a v ss q3 a q2 a q1 a 13 14 15 16 9 10 11 12 5 4 3 2 1 8 7 6 q 0 b b b a b e b v dd q 3 b q 2 b q 1 b q 0 a b a a a e a v ss q 3 a q 2 a q 1 a mc14555b mc14556b truth table inputs outputs enable select mc14555b mc14556b e b a q3 q2 q1 q0 q 3q 2q 1q 0 0 0 0 0 0011110 0 0 1 0 0101101 0 1 0 0 1001011 0 1 1 1 0000111 1 x x 0 0001111 x = don't care block diagram 2 4 mc14555b mc14556b 3 1 14 13 15 5 6 7 12 11 10 9 2 4 3 1 14 13 15 5 6 7 12 11 10 9 v dd = pin 16 v ss = pin 8 a b e q0 q1 q2 q3 a b e q 0 q 1 q 2 q 3 a b e q0 q1 q2 q3 a b e q 0 q 1 q 2 q 3
mc14555b, mc14556b http://onsemi.com 3 ????????????????????????????????? ????????????????????????????????? electrical characteristics (voltages referenced to v ss ) v dd 55 c 25 c 125 c characteristic symbol v dd vdc min max min typ (4) max min max unit output voltage a0o level v in = v dd or 0 v ol 5.0 10 15 0.05 0.05 0.05 0 0 0 0.05 0.05 0.05 0.05 0.05 0.05 vdc a1o level v in = 0 or v dd v oh 5.0 10 15 4.95 9.95 14.95 4.95 9.95 14.95 5.0 10 15 4.95 9.95 14.95 vdc input voltage a0o level (v o = 4.5 or 0.5 vdc) (v o = 9.0 or 1.0 vdc) (v o = 13.5 or 1.5 vdc) v il 5.0 10 15 1.5 3.0 4.0 2.25 4.50 6.75 1.5 3.0 4.0 1.5 3.0 4.0 vdc a1o level (v o = 0.5 or 4.5 vdc) (v o = 1.0 or 9.0 vdc) (v o = 1.5 or 13.5 vdc) v ih 5.0 10 15 3.5 7.0 11 3.5 7.0 11 2.75 5.50 8.25 3.5 7.0 11 vdc output drive current (v oh = 2.5 vdc) source (v oh = 4.6 vdc) (v oh = 9.5 vdc) (v oh = 13.5 vdc) i oh 5.0 5.0 10 15 3.0 0.64 1.6 4.2 2.4 0.51 1.3 3.4 4.2 0.88 2.25 8.8 1.7 0.36 0.9 2.4 madc (v ol = 0.4 vdc) sink (v ol = 0.5 vdc) (v ol = 1.5 vdc) i ol 5.0 10 15 0.64 1.6 4.2 0.51 1.3 3.4 0.88 2.25 8.8 0.36 0.9 2.4 madc input current i in 15 0.1 0.00001 0.1 1.0 adc input capacitance (v in = 0) c in 5.0 7.5 pf quiescent current (per package) i dd 5.0 10 15 5.0 10 20 0.005 0.010 0.015 5.0 10 20 150 300 600 adc total supply current (5) (6) (dynamic plus quiescent, per package) (c l = 50 pf on all outputs, all buffers switching) i t 5.0 10 15 i t = (0.85 a/khz) f + i dd i t = (1.70 a/khz) f + i dd i t = (2.60 a/khz) f + i dd adc 4. data labelled atypo is not to be used for design purposes but is intended as an indication of the ic's potential performance. 5. the formulas given are for the typical characteristics only at 25 c. 6. to calculate total supply current at loads other than 50 pf: i t (c l ) = i t (50 pf) + (c l 50) vfk where: i t is in a (per package), c l in pf, v = (v dd v ss ) in volts, f in khz is input frequency, and k = 0.002.
mc14555b, mc14556b http://onsemi.com 4 ????????????????????????????????? ????????????????????????????????? switching characteristics (7) (c l = 50 pf, t a = 25 c) characteristic symbol v dd min typ (8) max unit output rise and fall time t tlh , t thl = (1.5 ns/pf) c l + 25 ns t tlh , t thl = (0.75 ns/pf) c l + 12.5 ns t tlh , t thl = (0.55 ns/pf) c l + 9.5 ns t tlh , t thl 5.0 10 15 100 50 40 200 100 80 ns propagation delay time a, b to output t plh , t phl = (1.7 ns/pf) c l + 135 ns t plh , t phl = (0.66 ns/pf) c l + 62 ns t plh , t phl = (0.5 ns/pf) c l + 45 ns t plh , t phl 5.0 10 15 220 95 70 440 190 140 ns propagation delay time e to output t plh , t phl = (1.7 ns/pf) c l + 115 ns t plh , t phl = (0.66 ns/pf) c l + 52 ns t plh , t phl = (0.5 ns/pf) c l + 40 ns t plh , t phl 5.0 10 15 200 85 65 400 170 130 ns 7. the formulas given are for the typical characteristics only at 25 c. 8. data labelled atypo is not to be used for design purposes but is intended as an indication of the ic's potential performance. figure 1. dynamic power dissipation signal waveforms figure 2. dynamic signal waveforms all 8 outputs connect to respective c l loads. f in respect to a system clock. input e low 20 ns 20 ns 90% 50% 10% 2f 1 v dd v ss v dd v ss v oh v ol a inputs (50% duty cycle) b inputs (50% duty cycle) output q1 20 ns 20 ns v dd v ss v oh v ol v oh v ol 90% 50% 10% 90% 50% 10% 90% 50% 10% t plh t tlh t phl t phl t thl t plh t tlh t thl input a high, input e low input b output q3 mc14556b output q3 mc14555b logic diagram (1/2 of dual) *eliminated for mc14555b * * * * q0 q1 q2 q3 e b a
mc14555b, mc14556b http://onsemi.com 5 package dimensions pdip16 p suffix plastic dip package case 64808 issue r notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. a b f c s h g d j l m 16 pl seating 18 9 16 k plane t m a m 0.25 (0.010) t dim min max min max millimeters inches a 0.740 0.770 18.80 19.55 b 0.250 0.270 6.35 6.85 c 0.145 0.175 3.69 4.44 d 0.015 0.021 0.39 0.53 f 0.040 0.70 1.02 1.77 g 0.100 bsc 2.54 bsc h 0.050 bsc 1.27 bsc j 0.008 0.015 0.21 0.38 k 0.110 0.130 2.80 3.30 l 0.295 0.305 7.50 7.74 m 0 10 0 10 s 0.020 0.040 0.51 1.01
mc14555b, mc14556b http://onsemi.com 6 package dimensions soic16 d suffix plastic soic package case 751b05 issue j notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 18 16 9 seating plane f j m r x 45 g 8 pl p b a m 0.25 (0.010) b s t d k c 16 pl s b m 0.25 (0.010) a s t dim min max min max inches millimeters a 9.80 10.00 0.386 0.393 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.229 0.244 r 0.25 0.50 0.010 0.019
mc14555b, mc14556b http://onsemi.com 7 package dimensions h e a 1 dim min max min max inches --- 2.05 --- 0.081 millimeters 0.05 0.20 0.002 0.008 0.35 0.50 0.014 0.020 0.18 0.27 0.007 0.011 9.90 10.50 0.390 0.413 5.10 5.45 0.201 0.215 1.27 bsc 0.050 bsc 7.40 8.20 0.291 0.323 0.50 0.85 0.020 0.033 1.10 1.50 0.043 0.059 0 0.70 0.90 0.028 0.035 --- 0.78 --- 0.031 a 1 h e q 1 l e 10 0 10 l e q 1 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions d and e do not include mold flash or protrusions and are measured at the parting line. mold flash or protrusions shall not exceed 0.15 (0.006) per side. 4. terminal numbers are shown for reference only. 5. the lead width dimension (b) does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the lead width dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. minimum space between protrusions and adjacent lead to be 0.46 ( 0.018). m l detail p view p c a b e m 0.13 (0.005) 0.10 (0.004) 1 16 9 8 d z e a b c d e e l m z soeiaj16 f suffix plastic eiaj soic package case 96601 issue o
mc14555b, mc14556b http://onsemi.com 8 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and re asonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employ er. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mc14555b/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada
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